The present disclose relates to a semiconductor structure and a method of forming the same. More particularly, the present disclosure relates to a dual gate extremely thin semiconductor-on-insulator (ETSOI) structure with back gate electrodes that are physically isolated, and a method of forming the ETSOI structure.
In order to be able to make integrated circuits (ICs), such as memory, logic, and other devices, of a higher integration density than is currently feasible, field effect transistor (FET) dimensions must be scaled down, as FETs are an important component of many ICs. However, as FET dimensions are scaled down, FETs may suffer from various problems. For example, interactions between the source and drain of the FET may degrade the ability to control whether the FET is on or off, which may result in memory or logic errors during IC operation. As the FET size is reduced, the distance between source and drain regions of the FET is decreased, leading to increased interaction with the channel by the source and drain, and reduced gate control of the channel. This phenomenon is referred to as the short channel effect. It becomes increasingly more difficult to control short channel effects by conventional techniques as FETs become smaller.
An evolution beyond the standard FET with a single top gate that controls the FET channel is the double-gated FET, wherein the channel is confined between a top and a bottom gate. Positioning the channel between a top and a bottom gate allows for control of the channel by the two gates from both sides of the channel, reducing short channel effects. Further, a double-gated FET may exhibit higher transconductance and reduced parasitic capacitance as compared to a single-gated FET. The presence of the back gate allows for enhanced on-chip power management and device tuning. Multiple threshold voltage (Vt) devices may also be achieved on a single IC chip by applying different back biases at the back gates of various devices.